SN54LVTH373, SN74LVTH373 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS689D - MAY 1997 - REVISED APRIL 1998

features

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
High-Impedance State During Power Up and Power Down
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Power Off Disables Outputs, Permitting Live Insertion
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs

description

These octal latches are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54LVTH373 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH373 is characterized for operation from -40°C to 85°C.

Title: 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) LATCHES
Device Functionality: OCTAL TRANSPARENT D-TYPE LATCH
Orderable Devices: SN74LVTH373DBLE, SN74LVTH373DW, SN74LVTH373DWR, SN74LVTH373PWLE

View the complete PDF datasheet: scbs689d.pdf (121 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVTH373

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