SN54LVT18502 3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 - JULY 1996

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features

• Member of the Texas Instruments SCOPE^TM Family of Testability Products
• Member of the Texas Instruments Widebus^TM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Supports Unregulated Battery Operation Down to 2.7 V
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SCOPE, Widebus, and UBT are trademarks of Texas InstrumentsIncorporated.

description

The SN54LVT18502 scan test device with 18-bit universal bustransceivers is a member of the Texas Instruments SCOPE^TMtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

Additionally, this device is designed specifically for low-voltage(3.3-V) V_CC operation, but with the capability to providea TTL interface to a 5-V system environment.

In the normal mode, this device is an 18-bit universal bustransceiver that combines D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. It can beused either as two 9-bit transceivers or one 18-bit transceiver. Thetest circuitry can be activated by the TAP to take snapshot samplesof the data appearing at the device pins or to perform a self test onthe boundary-test cells. Activating the TAP in the normal mode doesnot affect the functional operation of the SCOPE^TMuniversal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the deviceoperates in the transparent mode when LEAB is high. When LEAB is low,the A-bus data is latched while CLKAB is held at a static low or highlogic level. Otherwise, if LEAB is low, A-bus data is stored on alow-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow, but uses the , LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE^TMuniversal bus transceivers is inhibited and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operationsaccording to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry performs other testing functionssuch as parallel-signature analysis (PSA) on data inputs andpseudo-random pattern generation (PRPG) from data outputs. Alltesting and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

The SN54LVT18502 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C.

View more information about generic part numbers:SN54LVT18502

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