SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A,SN74LVTH182502A 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS668A - JULY 1996 - REVISED DECEMBER 1996

Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.

features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• B-Port Outputs of 'LVTH182502A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

description

The 'LVTH18502A and 'LVTH182502A scan test devices with 18-bituniversal bus transceivers are members of the Texas InstrumentsSCOPE^TM testability integrated-circuit family. This familyof devices supports IEEE Standard 1149.1-1990 boundary scan tofacilitate testing of complex circuit-board assemblies. Scan accessto the test circuitry is accomplished via the 4-wire test access port(TAP) interface.

Additionally, these devices are designed specifically forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bustransceivers that combine D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. They canbe used either as two 9-bit transceivers or one 18-bit transceiver.The test circuitry can be activated by the TAP to take snapshotsamples of the data appearing at the device pins or to perform a selftest on the boundary-test cells. Activating the TAP in the normalmode does not affect the functional operation of theSCOPE^TM universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the deviceoperates in the transparent mode when LEAB is high. When LEAB is low,the A-bus data is latched while CLKAB is held at a static low or highlogic level. Otherwise, if LEAB is low, A-bus data is stored on alow-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow, but uses the , LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE^TMuniversal bus transceivers is inhibited, and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operationsaccording to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry performs other testing functionssuch as parallel-signature analysis (PSA) on data inputs andpseudo-random pattern generation (PRPG) from data outputs. Alltesting and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

The B-port outputs of 'LVTH182502A, which are designed to sourceor sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18502A and SN54LVTH182502A are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74LVTH18502A and SN74LVTH182502A are characterizedfor operation from -40°C to 85°C.

View more information about generic part numbers:SN74LVTH182502A, SN74LVTH18502A

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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