SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A,SN74LVTH182504A 3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS667B - JULY 1996 - REVISED JUNE 1997

Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.

features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• B-Port Outputs of 'LVTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE Instruction Set
  • IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

  SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

description

The 'LVTH18504A and 'LVTH182504A scan test devices with 20-bituniversal bus transceivers are members of the Texas Instruments (TI)SCOPE testability integrated-circuit family. This family of devicessupports IEEE Std 1149.1-1990 boundary scan to facilitate testing ofcomplex circuit-board assemblies. Scan access to the test circuitryis accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bustransceivers that combine D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self-test on theboundary-test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPE universal bustransceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),clock-enable ( and ), and clock (CLKAB and CLKBA)inputs. For A-to-B data flow, the device operates in the transparentmode when LEAB is high. When LEAB is low, the A-bus data is latchedwhile is high and/orCLKAB is held at a static low or high logic level. Otherwise, if LEABis low and is low, A-busdata is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow, but uses the , LEBA,, andCLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bustransceivers is inhibited, and the test circuitry is enabled toobserve and control the I/O boundary of the device. When enabled, thetest circuitry performs boundary-scan test operations according tothe protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry performs other testing functions,such as parallel-signature analysis (PSA) on data inputs andpseudo-random pattern generation (PRPG) from data outputs. Alltesting and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

The B-port outputs of 'LVTH182504A, which are designed to sourceor sink up to 12 mA, include equivalent 25- series resistors to reduceovershoot and undershoot.

The SN54LVTH18504A and SN54LVTH182504A are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74LVTH18504A and SN74LVTH182504A are characterizedfor operation from -40°C to 85°C.

View more information about generic part numbers:SN74LVTH182504A, SN74LVTH18504A

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
Trademarks, Important Notice!