SN54ABT162823A, SN74ABT162823A 18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS666A - JULY 1996 - REVISED MAY 1997

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

Members of the Texas Instruments Widebus^TM Family
Output Ports Have Equivalent 25- Series Resistors So No External Resistors Are Required
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
High-Impedance State During Power Up and Power Down
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

description

These 18-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The 'ABT162823A can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN\) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, thus latching the outputs. Taking the clear (CLR\) input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE\) input places the nine outputs in either a normal logic state (high or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT162823A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162823A is characterized for operation from -40°C to 85°C.

Title: 18-BIT BUS- INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) FLIP-FLOPS
Device Functionality: 18-BIT BUS INTERFACE FLIP-FLOP
Orderable Devices: SN74ABT162823ADGGR, SN74ABT162823ADL, SN74ABT162823ADLR

View the complete PDF datasheet: scbs666a.pdf (128 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ABT162823A

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.