SCBS489B - AUGUST 1994 - REVISED DECEMBER 1996
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) Pin Forces Primary-to-Secondary Connection Without Use of Shadow Protocols 
) Pin Provides Indication of Primary-to-Secondary Connection
SCOPE is a trademark of Texas Instrumentsdescription
The 'ABT8996 10-bit addressable scan ports (ASP) are members ofthe Texas Instruments SCOPETM testabilityintegrated-circuit family. This family of devices supports IEEEStandard 1149.1-1990 boundary scan to facilitate testing of complexcircuit assemblies. Unlike most SCOPETM devices, the ASPis not a boundary-scannable device, rather, it applies TI'saddressable-shadow-port technology to the IEEE Standard 1149.1-1990(JTAG) test access port (TAP) to extend scan access beyond the boardlevel.
Conceptually, the ASP is a simple switch that can be used todirectly connect a set of multidrop primary TAP signals to a set ofsecondary TAP signals - for example, to interface backplane TAPsignals to a board-level TAP. The ASP provides all signal bufferingthat might be required at these two interfaces. When primary andsecondary TAPs are connected, only a moderate propagation delay isintroduced - no storage/retiming elements are inserted. Thisminimizes the need for reformatting board-level test vectors forin-system use.
Most operations of the ASP are synchronous to the primary testclock (PTCK) input. This PTCK signal is always buffered directly ontothe secondary test clock (STCK) output.
Upon power up of the device, the ASP assumes a condition in whichthe primary TAP is disconnected from the secondary TAP (unless thebypass signal is used, as below). This reset condition also can beentered by the assertion of the primary test reset (
signal isalways buffered directly onto the secondary test reset (
When connected, the primary test data input (PTDI) and primarytest mode select (PTMS) input are buffered onto the secondary testdata output (STDO) and secondary test mode select (STMS) output,respectively, while the secondary test data input (STDI) is bufferedonto the primary test data output (PTDO). When disconnected, STDO isat high impedance, while PTDO is at high impedance, except duringacknowledgement of a shadow protocol. Upon disconnect of thesecondary TAP, STMS holds its last low or high level, allowing thesecondary TAP to be held in its last stable state. Upon reset of theASP, STMS is high, allowing the secondary TAP to be synchronouslyreset to the Test-Logic-Reset state.
In system, primary-to-secondary connection is based on shadowprotocols that are received and acknowledged on PTDI and PTDO,respectively. These protocols can occur in any of the stable TAPstates other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset,Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of theprotocols is to receive/transmit an address via a serial bit-pairsignaling scheme. When an address is received serially at PTDI thatmatches that at the parallel address inputs (A9-A0), the ASP seriallyretransmits its address at PTDO as an acknowledgement and thenassumes the connected (ON) status, as above. If the received addressdoes not match that at the address inputs, the ASP immediatelyassumes the disconnected (OFF) status without acknowledgement.
The ASP also supports three dedicated addresses that can bereceived globally (that is, to which all ASPs respond) during shadowprotocols. Receipt of the dedicated disconnect address (DSA) causesthe ASP to disconnect in the same fashion as a non-matching address.Reservation of this address for global use ensures that at least oneaddress is available to disconnect all receiving ASPs. The DSA isespecially useful when the secondary TAPs of multiple ASPs are to beleft in different stable states. Receipt of the reset address (RSA)causes the ASP to assume the reset condition, as above. Receipt ofthe test-synchronization address (TSA) causes the ASP to assume aconnect status (MULTICAST) in which PTDO is at high impedance but theconnections from PTMS to STMS and PTDI to STDO are maintained toallow simultaneous operation of the secondary TAPs of multiple ASPs.This is useful for multicast TAP-state movement, simultaneous testoperation (such as in Run-Test/Idle state), and scanning of commontest data into multiple like scan chains. The TSA is valid only whenreceived in the Pause-DR or Pause-IR TAP states.
Alternatively, primary-to-secondary connection can be selected byassertion of a low level at the bypass () input. This operation is asynchronous to PTCK and isindependent of and/orpower-up reset. This bypassing feature is especially useful in theboard-test environment, since it allows the board-level automatedtest equipment (ATE) to treat the ASP as a simple transceiver. Whenthe input is high,the ASP is free to respond to shadow protocols. Otherwise, when
Whether the connected status is achieved by use of shadow protocolor by use of, this statusis indicated by a low level at the connect (
The SN54ABT8996 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT8996 is characterized for operation from -40°C to85°C.
View more information about generic part numbers:SN54ABT8996, SN74ABT8996
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