SCBS480G - JUNE 1994 - REVISED SEPTEMBER 1997
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These 18-bit bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
The B port operates at GTL levels while the A port and control inputs are compatible with LVTTL and 5-V TTL logic levels.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. The clock or latch-enable can be controlled by the clock-enable (CEAB\ and CEBA\) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CEAB\ is low and CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB\ also is low. OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but uses OEBA\, LEBA, CLKBA, and CEBA\.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16612 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74GTL16612 is characterized for operation from -40°C to 85°C.
View more information about generic part numbers:SN74GTL16612
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