SN54ABT18640, SN74ABT18640 SCAN TEST DEVICES WITH 18-BIT INVERTING BUS TRANSCEIVERS

SCBS267C - FEBRUARY 1994 - REVISED JULY 1996

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features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

  SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

description

The 'ABT18640 scan test devices with 18-bit inverting bustransceivers are members of the Texas Instruments SCOPE^TMtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are 18-bit inverting bustransceivers. They can be used either as two 9-bit transceivers orone 18-bit transceiver. The test circuitry can be activated by theTAP to take snapshot samples of the data appearing at the device pinsor to perform a self test on the boundary-test cells. Activating theTAP in the normal mode does not affect the functional operation ofthe SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) andoutput-enable () inputs. Datatransmission is allowed from the A bus to the B bus or from the B busto the A bus, depending on the logic level at DIR. can be used to disable the deviceso that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TMbus transceivers is inhibited and the test circuitry is enabled toobserve and control the I/O boundary of the device. When enabled, thetest circuitry can perform boundary-scan test operations according tothe protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of thetest circuitry: test data input (TDI), test data output (TDO), testmode select (TMS), and test clock (TCK). Additionally, the testcircuitry performs other testing functions such as parallel-signatureanalysis (PSA) on data inputs and pseudo-random pattern generation(PRPG) from data outputs. All testing and scan operations aresynchronized to the TAP interface.

The SN74ABT18640 is available in TI's shrink small-outline (DL)and thin shrink small-outline (DGG) packages, which provide twice theI/O pin count and functionality of standard small-outline packages inthe same printed-circuit-board area.

The SN54ABT18640 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT18640 is characterized for operation from -40°C to85°C.

View more information about generic part numbers:SN74ABT18640

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