SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED BUS TRANSCEIVERSWITH 3-STATE OUTPUTS

SCBS230F - JUNE 1992 - REVISED MAY 1997

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features

Members of the Texas Instruments Widebus+^TM Family
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 5 V, T_A = 25°C
High-Impedance State During Power Up and Power Down
Released as DSCC SMD 5962-9557801NXD
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14 × 14-mm Body Using 0.5-mm Lead Pitch and Space-Saving 100-Pin Ceramic Quad Flat (HS) Package
Widebus+ and EPIC-IIB are trademarks of Texas Instruments Incorporated.
The HS package is not production released.

description

The 'ABTH32543 are 36-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction. These devices can be used as two 18-bit transceivers or one 36-bit transceiver. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ABTH32543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH32543 is characterized for operation from -40°C to 85°C

Title: 36-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: 36-BIT REGISTERED BUS TRANSCEIVER
Orderable Devices: SN74ABTH32543PZ

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View more information about generic part numbers:SN54ABTH32543, SN74ABTH32543

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