SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F - FEBRUARY 1991 - REVISED OCTOBER 1997

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features

State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JESD 17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
High-Impedance State During Power Up and Power Down
Parity-Error Flag With Parity Generator/Checker
Latch for Storage of Parity-Error Flag
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs
EPIC-IIB is a trademark of Texas Instruments Incorporated.

description

The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Title: 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: PARITY TRANSCEIVERS
Orderable Devices: SNJ54ABT853FK, SNJ54ABT853JT, SNJ54ABT853W, SN74ABT853DBLE, SN74ABT853DW, SN74ABT853DWR, SN74ABT853NT, SN74ABT853PWLE

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View more information about generic part numbers:SN54ABT853, SN74ABT853

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