SN54ABTH18652A, SN54ABTH182652A, SN74ABTH18652A,SN74ABTH182652A SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS

SCBS167D - AUGUST 1993 - REVISED JULY 1996

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features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• B-Port Outputs of 'ABTH182652A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• State-of-the-Art EPIC-IIB^TM BiCMOS Design
• One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

   

   

description

The 'ABTH18652A and 'ABTH182652A scan test devices with 18-bit bustransceivers and registers are members of the Texas InstrumentsSCOPE^TM testability integrated-circuit family. This familyof devices supports IEEE Standard 1149.1-1990 boundary scan tofacilitate testing of complex circuit-board assemblies. Scan accessto the test circuitry is accomplished via the 4-wire test access port(TAP) interface.

In the normal mode, these devices are 18-bit bus transceivers andregisters that allow for multiplexed transmission of data directlyfrom the input bus or from the internal registers. They can be usedeither as two 9-bit transceivers or one 18-bit transceiver. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary-test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPE^TM bustransceivers and registers.

Data flow in each direction is controlled by clock (CLKAB andCLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow,data on the A bus is clocked into the associated registers on thelow-to-high transition of CLKAB. When SAB is low, real-time A data isselected for presentation to the B bus (transparent mode). When SABis high, stored A data is selected for presentation to the B bus(registered mode). When OEAB is high, the B outputs are active. WhenOEAB is low, the B outputs are in the high-impedance state. Controlfor B-to-A data flow is similar to that for A-to-B data flow, butuses CLKBA, SBA, and inputs. Since the input isactive-low, the A outputs are active when is low and are in thehigh-impedance state when ishigh. Figure 1 illustrates the four fundamental bus-managementfunctions that are performed with the 'ABTH18652A and 'ABTH182652A.

In the test mode, the normal operation of the SCOPE^TMbus transceivers and registers is inhibited, and the test circuitryis enabled to observe and control the I/O boundary of the device.When enabled, the test circuitry performs boundary-scan testoperations according to the protocol described in IEEE Standard1149.1-1990.

Four dedicated test pins observe and control the operation of thetest circuitry: test data input (TDI), test data output (TDO), testmode select (TMS), and test clock (TCK). Additionally, the testcircuitry performs other testing functions such as parallel-signatureanalysis (PSA) on data inputs and pseudo-random pattern generation(PRPG) from data outputs. All testing and scan operations aresynchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of aone boundary-scan cell (BSC) per I/O pin architecture. Thisarchitecture is implemented in such a way as to capture the mostpertinent test data. A PSA/COUNT instruction is also included to easethe testing of memories and other circuits where a binary countaddressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs ata valid logic level.

The B-port outputs of 'ABTH182652A, which are designed to sourceor sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54ABTH18652A and SN54ABTH182652A are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74ABTH18652A and SN74ABTH182652A are characterizedfor operation from -40°C to 85°C.

View more information about generic part numbers:SN74ABTH182652A, SN74ABTH18652A

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