SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A,SN74ABTH182504A SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS165C - AUGUST 1993 - REVISED JULY 1996

Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.

features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• B-Port Outputs of 'ABTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design
• One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
• SCOPE ^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of TexasInstruments Incorporated.

description

The 'ABTH18504A and 'ABTH182504A scan test devices with 20-bituniversal bus transceivers are members of the Texas InstrumentsSCOPE^TM testability integrated-circuit family. This familyof devices supports IEEE Standard 1149.1-1990 boundary scan tofacilitate testing of complex circuit-board assemblies. Scan accessto the test circuitry is accomplished via the 4-wire test access port(TAP) interface.

In the normal mode, these devices are 20-bit universal bustransceivers that combine D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary-test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPE^TM universalbus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),clock-enable ( and ), and clock (CLKAB and CLKBA)inputs. For A-to-B data flow, the device operates in the transparentmode when LEAB is high. When LEAB is low, the A-bus data is latchedwhile is high and/orCLKAB is held at a static low or high logic level. Otherwise, if LEABis low and is low, A-busdata is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow, but uses the , LEBA, , andCLKBA inputs.

In the test mode, the normal operation of the SCOPE^TMuniversal bus transceivers is inhibited, and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operationsaccording to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of thetest circuitry: test data input (TDI), test data output (TDO), testmode select (TMS), and test clock (TCK). Additionally, the testcircuitry performs other testing functions such as parallel-signatureanalysis (PSA) on data inputs and pseudo-random pattern generation(PRPG) from data outputs. All testing and scan operations aresynchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of aone boundary-scan cell (BSC) per I/O pin architecture. Thisarchitecture is implemented in such a way as to capture the mostpertinent test data. A PSA/COUNT instruction also is included to easethe testing of memories and other circuits where a binary countaddressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs ata valid logic level.

The B-port outputs of 'ABTH182504A, which are designed to sourceor sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54ABTH18504A and SN54ABTH182504A are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74ABTH18504A and SN74ABTH182504A are characterizedfor operation from -40°C to 85°C.

A-to-B data flow is shown. B-to-A data flow is similar butuses OEBA\, LEBA, CLKENBA\, and CLKBA.

Output level before the indicated steady-state inputconditions were established

View more information about generic part numbers:SN74ABTH182504A, SN74ABTH18504A

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