SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A,SN74ABTH182502A SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS164E - AUGUST 1993 - REVISED DECEMBER 1996

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features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Members of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
• B-Port Outputs of 'ABTH182502A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• State-of-the-Art EPIC-IIB^TM BiCMOS Design
• One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
• SCOPE Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

   

   

description

The 'ABTH18502A and 'ABTH182502A scan test devices with 18-bituniversal bus transceivers are members of the Texas Instruments SCOPEtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are 18-bit universal bustransceivers that combine D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. They canbe used either as two 9-bit transceivers or one 18-bit transceiver.The test circuitry can be activated by the TAP to take snapshotsamples of the data appearing at the device pins or to perform a selftest on the boundary-test cells. Activating the TAP in the normalmode does not affect the functional operation of the SCOPE universalbus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the deviceoperates in the transparent mode when LEAB is high. When LEAB is low,the A-bus data is latched while CLKAB is held at a static low or highlogic level. Otherwise, if LEAB is low, A-bus data is stored on alow-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow but uses the , LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bustransceivers is inhibited and the test circuitry is enabled toobserve and control the I/O boundary of the device. When enabled, thetest circuitry performs boundary-scan test operations according tothe protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of thetest circuitry: test data input (TDI), test data output (TDO), testmode select (TMS), and test clock (TCK). Additionally, the testcircuitry performs other testing functions such as parallel-signatureanalysis (PSA) on data inputs and pseudo-random pattern generation(PRPG) from data outputs. All testing and scan operations aresynchronized to the TAP interface.

Improved scan efficiency is accomplished through the adoption of aone boundary-scan cell (BSC) per I/O pin architecture. Thisarchitecture is implemented in such a way as to capture the mostpertinent test data. A PSA/COUNT instruction also is included to easethe testing of memories and other circuits where a binary countaddressing scheme is useful.

Active bus-hold circuitry holds unused or floating data inputs ata valid logic level.

The B-port outputs of 'ABTH182502A, which are designed to sourceor sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54ABTH18502A and SN54ABTH182502A are characterized foroperation over the full military temperature range of -55°C to125°C. The SN74ABTH18502A and SN74ABTH182502A are characterizedfor operation from -40°C to 85°C.

A-to-B data flow is shown. B-to-A data flow is similar butuses OEBA\, LEBA, and CLKBA.

Output level before the indicated steady-state inputconditions were established

View more information about generic part numbers:SN54ABTH18502A, SN74ABTH182502A, SN74ABTH18502A

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