SN74LVT18504 3.3-V ABT SCAN TEST DEVICE WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS163F - AUGUST 1993 - REVISED JULY 1996

features

• Member of the Texas Instruments SCOPE ^TM Family of Testability Products
• Member of the Texas Instruments Widebus^TM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Supports Unregulated Battery Operation Down to 2.7 V
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE ^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat Packages Using 0.5-mm Center-to-Center Spacings

  SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

   

description

The SN74LVT18504 scan test device with 20-bit universal bustransceivers is a member of the Texas Instruments SCOPE^TMtestability integrated circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

Additionally, this device is designed specifically for low-voltage(3.3-V) V_CC operation, but with the capability to providea TTL interface to a 5-V system environment.

In the normal mode, this device is a 20-bit universal bustransceiver that combines D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary-test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPE^TM universalbus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),clock-enable ( and ), and clock (CLKAB and CLKBA)inputs. For A-to-B data flow, the device operates in the transparentmode when LEAB is high. When LEAB is low, the A-bus data is latchedwhile is high and/orCLKAB is held at a static low or high logic level. Otherwise, if LEABis low and is low, A-busdata is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow but uses the , LEBA, , andCLKBA inputs.

In the test mode, the normal operation of the SCOPE^TMuniversal bus transceivers is inhibited and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operationsaccording to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry performs other testing functionssuch as parallel-signature analysis (PSA) on data inputs andpseudo-random pattern generation (PRPG) from data outputs. Alltesting and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

The SN74LVT18504 is characterized for operation from -40°C to85°C.

View more information about generic part numbers:SN74LVT18504

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