SN54ABT16853, SN74ABT16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS153B - OCTOBER 1992 - REVISED JANUARY 1997

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features

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Parity-Error Flag With Parity Generator/Checker
Latch for Storage of the Parity-Error Flag
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

EPIC-IIB and Widebus are trademarks of Texas Instruments Incorporated.

description

The 'ABT16853 dual 8-bit to 9-bit parity transceivers are designedfor communication between data buses. When data is transmitted fromthe A bus to the B bus, a parity bit is generated. When data istransmitted from the B bus to the A bus, with its correspondingparity bit, the open-collector parity-error () output indicates whether or notan error in the B data has occurred. The output-enable (and ) inputs can be used to disable thedevice so that the buses are effectively isolated. The 'ABT16853provide true data at the outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY)output and monitors the parity of the I/O ports with the flag. The parity-error output canbe passed, sampled, stored, or cleared from the latch using thelatch-enable () and clear() controlinputs. When both and are low, data is transferred fromthe A bus to the B bus, and inverted parity is generated. Invertedparity is a forced error condition that gives the designer moresystem diagnostic capability.

To ensure the high-impedance state during power up or power down, should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver.

The SN54ABT16853 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT16853 is characterized for operation from -40°C to85°C.

Title: DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Product Family: PARITY TRANSCEIVERS
Device Functionality: PARITY BUS TRANSCEIVER
Orderable Devices: SN74ABT16853DGGR, SN74ABT16853DL, SN74ABT16853DLR

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View more information about generic part numbers:SN74ABT16853

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