SN54LVT16543, SN74LVT16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS148C - MAY 1992 - REVISED JULY 1995

features

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation
Members of the Texas Instruments Widebus^TM Family
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC = 3.3 V, T_A = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
Support Live Insertion
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus is a trademark of Texas Instruments Incorporated.

description

The 'LVT16543 are 16-bit registered transceivers designed forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment. These devicescan be used as two 8-bit transceivers or one 16-bit transceiver.Separate latch-enable (or) andoutput-enable ( or ) inputs are provided for eachregister to permit independent control in either direction of dataflow.

The A-to-B enable ()input must be low in order to enter data from A or to output datafrom B. If is low and is low, theA-to-B latches are transparent; a subsequent low-to-high transitionof puts the Alatches in the storage mode. With and both low, the3-state B outputs are active and reflect the data present at theoutput of the A latches. Data flow from B to A is similar butrequires using the ,, and inputs.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver.

The SN74LVT16543 is available in TI's shrink small-outline (DL)and thin shrink small-outline (DGG) packages, which provide twice theI/O pin count and functionality of standard small-outline packages inthe same printed-circuit-board area.

The SN54LVT16543 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74LVT16543 is characterized for operation from -40°C to85°C.

Title: 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
Product Family: LATCHED TRANSCEIVERS
Device Functionality: 16-BIT REGISTERED BUS TRANSCEIVER
Orderable Devices: SN74LVT16543DGGR, SN74LVT16543DL, SN74LVT16543DLR

View the complete PDF datasheet: scbs148c.pdf (137 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVT16543

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