SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SCBS146D - MAY 1992 - REVISED NOVEMBER 1996

Please be aware that an important notice concerningavailability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers theretoappears at the end of this data sheet.

features

• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation
• Members of the Texas Instruments Widebus^TM Family
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• UBT^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Support Live Insertion
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB Layout
• Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

  Widebus and UBT are trademarks of Texas Instruments Incorporated.

   

description

The 'LVT16500 are 18-bit universal bus transceivers designed forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment.

Data flow in each direction is controlled by output-enable (OEABand ), latch-enable(LEAB and LEBA), and clock ( and) inputs. ForA-to-B data flow, the device operates in the transparent mode whenLEAB is high. When LEAB is low, the A data is latched if is held at a high or low logiclevel. If LEAB is low, the A-bus data is stored in thelatch/flip-flop on the high-to-low transition of . Output-enable OEAB is activehigh. When OEAB is high, the B-port outputs are active. When OEAB islow, the B-port outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses , LEBA, and . The output enables arecomplementary (OEAB is active high and OEBA\ is active low).

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

To ensure the high-impedance state during power up or power down,should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver. OE should be tied to GND through a pulldown resistor; theminimum value of the resistor is determined by the current-sourcingcapability of the driver.

The SN74LVT16500 is available in TI's shrink small-outline (DL)and thin shrink small-outline (DGG) packages, which provide twice theI/O pin count and functionality of standard small-outline packages inthe same printed circuit board area.

The SN54LVT16500 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74LVT16500 is characterized for operation from -40°C to85°C.

A-to-B data flow is shown: B-to-A flow is similar but usesOEBA\, LEBA, and CLKBA\.

Output level before the indicated steady-state inputconditions were established

^§ Output level before the indicatedsteady-state input conditions were established, provided that CLKAB\was low before LEAB went low

View more information about generic part numbers:SN74LVT16500

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(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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