SN54LVTH16374, SN74LVTH16374 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SCBS145K - MAY 1992 - REVISED APRIL 1998

features

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
High-Impedance State During Power Up and Power Down
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Power Off Disables Outputs, Permitting Live Insertion
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JESD 17
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus is a trademark of Texas Instruments Incorporated.

description

The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54LVTH16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH16374 is characterized for operation from -40°C to 85°C.

Title: 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) FLIP-FLOPS
Device Functionality: 16-BIT D-TYPE FLIP-FLOP
Orderable Devices: SN74LVTH16374DGGR, SN74LVTH16374DL, SN74LVTH16374DLR

View the complete PDF datasheet: scbs145k.pdf (118 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54LVTH16374, SN74LVTH16374

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