SN54LVT652, SN74LVT652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SCBS141E - MAY 1992 - REVISED JULY 1995

features

• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
• Support Live Insertion
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs

description

These bus transceivers and registers are designed specifically forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment.

The 'LVT652 consist of bus transceiver circuits, D-typeflip-flops, and control circuitry arranged for multiplexedtransmission of data directly from the data bus or from the internalstorage registers.

Output-enable (OEAB and )inputs are provided to control the transceiver functions.Select-control (SAB and SBA) inputs are provided to select whetherreal-time or stored data is transferred. The circuitry used forselect control eliminates the typical decoding glitch that occurs ina multiplexer during the transition between real-time and storeddata. A low input selects real-time data and a high input selectsstored data. Figure 1 illustrates the four fundamental bus-managementfunctions that can be performed with the ´LVT652.

Data on the A or B data bus, or both, can be stored in theinternal D-type flip-flops by low-to-high transitions at theappropriate clock (CLKAB or CLKBA) inputs regardless of the select-or enable-control pins. When SAB and SBA are in the real-timetransfer mode, it is possible to store data without using theinternal D-type flip-flops by simultaneously enabling OEAB and . In this configuration, eachoutput reinforces its input; therefore, when all other data sourcesto the two sets of bus lines are at high impedance, each set of buslines remains at its last state.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

To ensure the high-impedance state during power up or power down,should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver. OE should be tied to GND through a pulldown resistor; theminimum value of the resistor is determined by the current-sourcingcapability of the driver.

The SN74LVT652 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.

The SN54LVT652 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74LVT652 is characterized for operation from -40°C to85°C.

The data output functions may be enabled or disabled by avariety of level combinations at the OEAB or OEBA\ inputs. Data inputfunctions are always enabled; i.e., data at the bus pins is stored onevery low-to-high transition of the clock inputs.

Select control = L; clocks can occur simultaneously Select control = H; clocks must be staggered in order to load bothregisters

Figure 1. Bus-Management Functions

Pin numbers shown are for the DB, DW, JT, and PWpackages.

View more information about generic part numbers:SN74LVT652

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