SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SCBS140D - MAY 1992 - REVISED JULY 1995

features

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC = 3.3 V, T_A = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Packages, and Ceramic (JT) DIPs

description

These bus transceivers and registers are designed specifically forlow-voltage (3.3-V) V_CC operation, but with the capabilityto provide a TTL interface to a 5-V system environment.

The 'LVT646 consist of bus transceiver circuits, D-typeflip-flops, and control circuitry arranged for multiplexedtransmission of data directly from the input bus or from the internalregisters. Data on the A or B bus is clocked into the registers onthe low-to-high transition of the appropriate clock (CLKAB or CLKBA)input. Figure 1 illustrates the four fundamental bus-managementfunctions that can be performed with the ´LVT646.

Output-enable anddirection-control (DIR) inputs are provided to control thetransceiver functions. In the transceiver mode, data present at thehigh-impedance port may be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored andreal-time (transparent mode) data. The direction control (DIR)determines which bus receives data when is low. In the isolation mode( high), A datamay be stored in one register and/or B data may be stored in theother register.

When an output function is disabled, the input function is stillenabled and may be used to store and transmit data. Only one of thetwo buses, A or B, may be driven at a time.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver.

The SN74LVT646 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.

The SN54LVT646 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74LVT646 is characterized for operation from -40°C to85°C.

Title: 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
Product Family: REGISTERED TRANSCEIVERS
Device Functionality: OCTAL BUS TRANSCEIVER
Orderable Devices: SNJ54LVT646FK, SNJ54LVT646JT, SNJ54LVT646W, SN74LVT646DBLE, SN74LVT646DW, SN74LVT646DWR, SN74LVT646PWLE

View the complete PDF datasheet: scbs140d.pdf (145 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54LVT646, SN74LVT646

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