SN54LVT573, SN74LVT573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCBS138D - MAY 1992 - REVISED JULY 1995

features

State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Support Unregulated Battery Operation Down to 2.7 V
Typical V_OLP (Output Ground Bounce)< 0.8 V at V_CC = 3.3 V, T_A = 25°C
ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Packages, and Ceramic (J) DIPs

description

These octal latches are designed specifically for low-voltage(3.3-V) V_CC operation, but with the capability to providea TTL interface to a 5-V system environment.

The eight latches of the 'LVT573 are transparent D-type latches.While the latch-enable (LE) input is high, the Q outputs follow thedata (D) inputs. When LE is taken low, the Q outputs are latched atthe logic levels set up at the D inputs.

A buffered output-enable input can be used to place the eight outputs in either a normal logicstate (high or low logic levels) or a high-impedance state. In thehigh-impedance state, the outputs neither load nor drive the buslines significantly. The high-impedance state and increased driveprovide the capability to drive bus lines without need for interfaceor pullup components. does not affect theinternal operations of the latches. Old data can be retained or newdata can be entered while the outputs are in the high-impedancestate.

Active bus-hold circuitry is provided to hold unused or floatingdata inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver.

The SN74LVT573 is available in TI's shrink small-outline package(DB), which provides the same I/O pin count and functionality ofstandard small-outline packages in less than half theprinted-circuit-board area.

The SN54LVT573 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74LVT573 is characterized for operation from -40°C to85°C.

Title: 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) LATCHES
Device Functionality: OCTAL D-TYPE LATCH
Orderable Devices: SNJ54LVT573FK, SNJ54LVT573J, SNJ54LVT573W, SN74LVT573DBLE, SN74LVT573DW, SN74LVT573DWR, SN74LVT573PWLE

View the complete PDF datasheet: scbs138d.pdf (102 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54LVT573, SN74LVT573

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