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Data Sheet Abstract

SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS

SCBS132A - AUGUST 1992 - REVISED OCTOBER 1992


features

description

The SN54ABT18652 and SN74ABT18652 scan test devices with 18-bitbus transceivers and registers are members of the Texas InstrumentsSCOPETM testability IC family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are 18-bit bus transceivers andregisters that allow for multiplexed transmission of data directlyfrom the input bus or from the internal registers. They can be usedeither as two 9-bit transceivers or one 18-bit transceiver. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPETM bustransceivers and registers.

Data flow in each direction is controlled by clock (CLKAB andCLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow,data on the A bus is clocked into the associated registers on thelow-to-high transition of CLKAB. When SAB is low, real-time A data isselected for presentation to the B bus (transparent mode). When SABis high, stored A data is selected for presentation to the B bus(registered mode). When OEAB is high, the B outputs are active. WhenOEAB is low, the B outputs are in the high-impedance state. Controlfor B-to-A data flow is similar to that for A-to-B data flow but usesCLKBA, SBA, and inputs. Sincethe input isactive-low, the A outputs are active when is low and are in thehigh-impedance state when ishigh. Figure 1 illustrates the four fundamental bus-managementfunctions that can be performed with the ´ABT18652.

 

In the test mode, the normal operation of the SCOPETMbus transceivers and registers is inhibited, and the test circuitryis enabled to observe and control the I/O boundary of the device.When enabled, the test circuitry can perform boundary scan testoperations according to the protocol described in IEEE Standard1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry can perform other testing functionssuch as parallel signature analysis on data inputs and pseudo-randompattern generation from data outputs. All testing and scan operationsare synchronized to the TAP interface.

Additional flexibility is provided in the test mode through theuse of two boundary scan cells (BSCs) for each I/O pin. This allowsindependent test data to be captured and forced at either bus (A orB). A PSA/COUNT instruction is also included to ease the testing ofmemories and other circuits where a binary count addressing scheme isuseful.

The SN54ABT18652 is characterized over the full militarytemperature range of -55°C to 125°C. The SN74ABT18652 ischaracterized for operation from -40°C to 85°C.

 

 


Title: SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS
Product Family: REGISTERED TRANSCEIVERS
Device Functionality: 18-BIT SCAN TEST TRANSCEIVER
Orderable Devices: SN74ABT18652PM

View the complete PDF datasheet: scbs132a.pdf (158 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ABT18652

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