SN74ABT3613 64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING

SCBS128F - JULY 1992 - REVISED APRIL 1998

features

• Low-Power Advanced BiCMOS Technology
• Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
• 64 × 36 FIFO Buffering Data From Port A to Port B
• Mailbox-Bypass Registers in Each Direction
• Dynamic Port-B Bus Sizing of 36 Bits (Long Word), 18 Bits (Word), and 9 Bits (Byte)
• Selection of Big- or Little-Endian Format for Word and Byte Bus Sizes
• Three Modes of Byte-Order Swapping on Port B
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor Interface Control Logic
• FF\ and AF\ Flags Synchronized by CLKA
• EF\ and AE\ Flags Synchronized by CLKB
• Passive Parity Checking on Each Port
• Parity Generation Can Be Selected for Each Port
• Supports Clock Frequencies up to 67 MHz
• Fast Access Times of 10 ns
• Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Quad Flat (PQ) Packages

description

The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO in this device buffers data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses controlled by a synchronous interface.

The full flag (FF\) and almost-full (AF\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The empty flag (EF\) and almost-empty (AE\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array.

The SN74ABT3613 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

• FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007)
• Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications (literature number SCAA014)
• Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications (literature number SCAA015)
• Internetworking the SN74ABT3614 (literature number SCAA018)
• Metastability Performance of Clocked FIFOs (literature number SCZA004)

View more information about generic part numbers:SN74ABT3613, SN74ABT3613-15, SN74ABT3613-20, SN74ABT3613-30

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