SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F - AUGUST 1992 - REVISED DECEMBER 1996

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features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Functionally Equivalent to 'F652 and 'ABT652 in the Normal-Function Mode
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
  • Parallel-Signature Analysis at Inputs With Masking Option
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Even-Parity Opcodes
• Two Boundary-Scan Cells Per I/O for Greater Flexibility
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

SCOPE and EPIC-IIB are trademarks of Texas InstrumentsIncorporated.

description

The 'ABT8652 scan test devices with octal bus transceivers andregisters are members of the Texas Instruments SCOPE^TMtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are functionally equivalent tothe 'F652 and 'ABT652 octal bus transceivers and registers. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary-test cells. Activating the TAP in normal mode does notaffect the functional operation of the SCOPE^TM octal bustransceivers and registers.

Data flow in each direction is controlled by clock (CLKAB andCLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow,data on the A bus is clocked into the associated registers on thelow-to-high transition of CLKAB. When SAB is low, real-time A data isselected for presentation to the B bus (transparent mode). When SABis high, stored A data is selected for presentation to the B bus(registered mode). When OEAB is high, the B outputs are active. WhenOEAB is low, the B outputs are in the high-impedance state. Controlfor B-to-A data flow is similar to that for A-to-B data flow but usesCLKBA, SBA, and inputs. Sincethe input isactive low, the A outputs are active when is low and are in thehigh-impedance state when ishigh. Figure 1 shows the four fundamental bus-management functionsthat can be performed with the 'ABT8652.

In the test mode, the normal operation of the SCOPE^TMbus transceivers and registers is inhibited and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operations asdescribed in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the testcircuitry: test data input (TDI), test data output (TDO), test modeselect (TMS), and test clock (TCK). Additionally, the test circuitryperforms other testing functions such as parallel-signature analysis(PSA) on data inputs and pseudo-random pattern generation (PRPG) fromdata outputs. All testing and scan operations are synchronized to theTAP interface.

The SN54ABT8652 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT8652 is characterized for operation from -40°C to85°C.

View more information about generic part numbers:SN54ABT8652, SN74ABT8652

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