SN54ABT8952, SN74ABT8952 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS121D - AUGUST 1992 - REVISED JULY 1996

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features

• Members of the Texas Instruments SCOPE^TM Family of Testability Products
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• Functionally Equivalent to 'BCT2952 and 'ABT2952 in the Normal-Function Mode
• SCOPE^TM Instruction Set
• IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
• Parallel-Signature Analysis at Inputs With Masking Option
• Pseudo-Random Pattern Generation From Outputs
• Sample Inputs/Toggle Outputs
• Binary Count From Outputs
• Even-Parity Opcodes
• Two Boundary-Scan Cells Per I/O for Greater Flexibility
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

SCOPE and EPIC-IIB are trademarks of Texas InstrumentsIncorporated.

description

The 'ABT8952 scan test devices with octal registered bustransceivers are members of the Texas Instruments SCOPE^TMtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are functionally equivalent tothe 'BCT2952 and 'ABT2952 octal registered bus transceivers. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self-test on theboundary-test cells. Activating the TAP in normal mode does notaffect the functional operation of the SCOPE^TM octalregistered bus transceivers.

Data flow in each direction is controlled by clock (CLKAB andCLKBA), clock-enable ( and), andoutput-enable ( and ) inputs. For A-to-B data flow,A-bus data is stored in the associated registers on the low-to-hightransition of CLKAB, provided that is low. Otherwise, if is high or CLKAB remains at a static low or high level,the register contents are not changed. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. Control for B-to-A data flowis similar to that for A-to-B, but uses CLKBA, , and .

In the test mode, the normal operation of the SCOPE^TMregistered bus transceivers is inhibited, and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operations asdescribed in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the testcircuitry: test data input (TDI), test data output (TDO), test modeselect (TMS), and test clock (TCK). Additionally, the test circuitryperforms other testing functions such as parallel signature analysis(PSA) on data inputs and pseudo-random pattern generation (PRPG) fromdata outputs. All testing and scan operations are synchronized to theTAP interface.

The SN54ABT8952 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT8952 is characterized for operation from -40°C to85°C.

View more information about generic part numbers:SN74ABT8952

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