SN54ABT8543, SN74ABT8543 SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS

SCBS120E - AUGUST 1991 - REVISED JULY 1996

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features

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
Functionally Equivalent to 'F543 and 'ABT543 in the Normal-Function Mode
SCOPE^TM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
Two Boundary-Scan Cells Per I/O for Greater Flexibility
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DL) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

SCOPE and EPIC-IIB are trademarks of Texas Instruments

description

The 'ABT8543 scan test devices with octal registered bustransceivers are members of the Texas Instruments SCOPE^TMtestability integrated-circuit family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit-board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are functionally equivalent tothe 'F543 and 'ABT543 octal registered bus transceivers. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self-test on theboundary-test cells. Activating the TAP in normal mode does notaffect the functional operation of the SCOPE^TM octalregistered bus transceivers.

Data flow in each direction is controlled by latch-enable ( and ), chip-enable ( and ), and output-enable ( and ) inputs. For A-to-B data flow, thedevice operates in the transparent mode when and are both low. When either or is high, the A data is latched.The B outputs are active when and are both low.When either or is high, the B outputs are in thehigh-impedance state. Control for B-to-A data flow is similar to thatfor A-to-B, but uses ,, and .

In the test mode, the normal operation of the SCOPE^TMregistered bus transceiver is inhibited and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary-scan test operations asdescribed in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the testcircuitry: test data input (TDI), test data output (TDO), test modeselect (TMS), and test clock (TCK). Additionally, the test circuitryperforms other testing functions such as parallel-signature analysis(PSA) on data inputs and pseudo-random pattern generation (PRPG) fromdata outputs. All testing and scan operations are synchronized to theTAP interface.

The SN54ABT8543 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT8543 is characterized for operation from -40°C to85°C.

Title: SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANCEIVERS
Product Family: BUS DEVICES
Device Functionality: OCTAL SCAN TEST, REGISTERED TRANSCEIVER
Orderable Devices: SNJ54ABT8543FK, SNJ54ABT8543JT, SN74ABT8543DL, SN74ABT8543DLR, SN74ABT8543DW, SN74ABT8543DWR

View the complete PDF datasheet: scbs120e.pdf (333 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN54ABT8543, SN74ABT8543

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