SN54ABT18504, SN74ABT18504 SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS108B - AUGUST 1992 - REVISED JUNE 1993

features

• Members of the Texas Instruments SCOPE ^TM Family of Testability Products
• Members of the Texas Instruments Widebus ^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• UBT ^TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Two Boundary-Scan Cells per I/O for Greater Flexibility
• State-of-the-Art EPIC-IIB ^TM BiCMOS Design Significantly Reduces Power Dissipation
• SCOPE ^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ
  • Parallel Signature Analysis at Inputs With Masking Option
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• Packaged in 64-Pin Plastic Thin Quad Flat Pack Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat Pack Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

   

   

description

The SN54ABT18504 and SN74ABT18504 scan test devices with 20-bituniversal bus transceivers are members of the Texas InstrumentsSCOPE^TM testability IC family. This family of devicessupports IEEE Standard 1149.1-1990 boundary scan to facilitatetesting of complex circuit board assemblies. Scan access to the testcircuitry is accomplished via the 4-wire test access port (TAP)interface.

In the normal mode, these devices are 20-bit universal bustransceivers that combine D-type latches and D-type flip-flops toallow data flow in transparent, latched, or clocked modes. The testcircuitry can be activated by the TAP to take snapshot samples of thedata appearing at the device pins or to perform a self test on theboundary test cells. Activating the TAP in the normal mode does notaffect the functional operation of the SCOPE^TM universalbus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),clock-enable ( and ), and clock (CLKAB and CLKBA)inputs. For A-to-B data flow, the device operates in the transparentmode when LEAB is high. When LEAB is low, the A-bus data is latchedwhile is high and/orCLKAB is held at a static low or high logic level. Otherwise, if LEABis low and is low, A-busdata is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active.When is high, the Boutputs are in the high-impedance state. B-to-A data flow is similarto A-to-B data flow but uses the , LEBA, , andCLKBA inputs.

In the test mode, the normal operation of the SCOPE^TMuniversal bus transceivers is inhibited, and the test circuitry isenabled to observe and control the I/O boundary of the device. Whenenabled, the test circuitry performs boundary scan test operationsaccording to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control theoperation of the test circuitry: test data input (TDI), test dataoutput (TDO), test mode select (TMS), and test clock (TCK).Additionally, the test circuitry can perform other testing functionssuch as parallel signature analysis on data inputs and pseudo-randompattern generation from data outputs. All testing and scan operationsare synchronized to the TAP interface.

Additional flexibility is provided in the test mode through theuse of two boundary scan cells (BSCs) for each I/O pin. This allowsindependent test data to be captured and forced at either bus (A orB). A PSA/COUNT instruction is also included to ease the testing ofmemories and other circuits where a binary count addressing scheme isuseful.

The SN54ABT18504 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT18504 is characterized for operation from -40°C to85°C.

View more information about generic part numbers:SN74ABT18504

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