SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS097D - FEBRUARY 1991 - REVISED JANUARY 1997

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features

Members of the Texas Instruments Widebus^TM Family
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
Parity-Error Flag With Parity Generator/Checker
Register for Storage of Parity-Error Flag
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

description

The 'ABT16833 consist of two noninverting 8-bit to 9-bit paritybus transceivers and are designed for communication between databuses. For each transceiver, when data is transmitted from the A busto the B bus, an odd-parity bit is generated and output on the parityI/O pin (1PARITY or 2PARITY). When data is transmitted from the B busto the A bus, 1PARITY (or 2PARITY) is configured as an input andcombined with the B-input data to generate an active-low error flagif odd parity is not detected.

The error (1 or 2) output is configured as anopen-collector output. The B-to-A parity-error flag is clocked into1 (or 2) on the low-to-high transition ofthe clock (1CLK or 2CLK) input. 1 (or 2) iscleared (set high) by taking the clear (1 or 2) input low.

The output-enable (and) inputs can beused to disable the device so that the buses are effectivelyisolated. When both andare low, datais transferred from the A bus to the B bus and inverted parity isgenerated. Inverted parity is a forced error condition that gives thedesigner more system diagnostic capability.

To ensure the high-impedance state during power up or power down, should be tiedto V_CC through a pullup resistor; the minimum value of theresistor is determined by the current-sinking capability of thedriver.

The SN54ABT16833 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. TheSN74ABT16833 is characterized for operation from -40°C to85°C.

Title: DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
Product Family: PARITY TRANSCEIVERS
Device Functionality: PARITY BUS TRANSCEIVER
Orderable Devices: SN74ABT16833DGGR, SN74ABT16833DL, SN74ABT16833DLR

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View more information about generic part numbers:SN74ABT16833

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