SN74BCT298538-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SCBS002D - SEPTEMBER 1987 - REVISED APRIL 1994

features

• BiCMOS Process With TTL Inputs and Outputs
• State-of-the-Art BiCMOS Design Significantly Reduces Standby Current
• Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
• Functionally Equivalent to AMD Am29853
• High-Speed Bus Transceiver With Parity Generator/Checker
• Parity-Error Flag With Open-Collector Output
• Latch for Storage of the Parity-Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)

description

The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designedfor asynchronous communication between data buses. When data istransmitted from the A to B bus, a parity bit is generated. When datais transmitted from the B to A bus with its corresponding parity bit,the parity-error () output willindicate whether or not an error in the B data has occurred. Theoutput-enable (, ) inputs can be used to disable thedevice so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY)output and monitors the parity of the I/O ports with anopen-collector parity-erro ()rflag. can be eitherpassed, sampled, stored, or cleared from the latch using thelatch-enable () and clear() controlinputs. When both and are low, data is transferred fromthe A bus to the B bus and inverted parity is generated. Invertedparity is a forced error condition which gives the designer moresystem diagnostic capability. The SN74BCT29853 provides true logic.

The SN74BCT29853 is characterized for operation from 0°C to70°C.

View more information about generic part numbers:SN74BCT29853

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