CDC2509A 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS603 - APRIL 1998

features

Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3-V V_CC
Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package

description

The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V V_CC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2509A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2509A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground.

The CDC2509A is characterized for operation from 0°C to 70°C.

Title: 3.3V PHASE LOCK LOOP CLOCK DRIVER
Product Family: OTHER DIGITAL LOGIC
Device Functionality: 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
Orderable Devices: CDC2509APWR

View the complete PDF datasheet: scas603.pdf (131 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:CDC2509A

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