SN74LVCH16373A 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SCAS568F - MARCH 1996 - REVISED JANUARY 1998

features

Member of the Texas Instruments Widebus^TM Family
EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
Power Off Disables Outputs, Permitting Live Insertion
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

EPIC and Widebus trademarks of Texas Instruments Incorporated.

description

This 16-bit transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVCH16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVCH16373A is characterized for operation from -40°C to 85°C.

Title: 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) LATCHES
Device Functionality: 16-BIT D-TYPE LATCH
Orderable Devices: SN74LVCH16373ADGGR, SN74LVCH16373ADGVR, SN74LVCH16373ADL, SN74LVCH16373ADLR

View the complete PDF datasheet: scas568f.pdf (89 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVCH16373A

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