CDC9843 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

SCAS559C - DECEMBER 1995 - REVISED OCTOBER 1996

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features

Provides System Clock Solution for Pentium^TM/82430HX/82430VX and PentiumPro 82440FX Chipsets
Four Host-Clock Outputs With Programmable Frequency (50 MHz, 60 MHz, and 66 MHz)
Six PCI Clock Outputs at Half-CPU Frequency
One 48-MHz Universal Serial Bus (USB) Clock Output
One 24-MHz Floppy Controller Output
Two 14.318-MHz Reference Clock Outputs
All Output Clock Frequencies Derived From Single 14.31818-MHz Crystal Input
LVTTL-Compatible Inputs and Outputs
Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components
Operates at 3.3-V V_CC
Packaged in Plastic Small-Outline Package
Pentium is a trademark of Intel Corporation.

description

The CDC9843 is a high-performance clock synthesizer/driver thatgenerates the system clocks necessary to supportPentium^TM/82430HX/82430VX and PentiumPro 82440FX chipsets.Four host-clock outputs (HCLKn) are programmable to one of threefrequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 controlinputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPUclock outputs and are delayed 1 ns to 4 ns from the rising edge ofthe CPU clock. In addition, a universal serial bus (USB) clock outputat 48 MHz (SBCLK), a floppy controller clock at 24 MHz (FCCLK), andtwo 14.318-MHz reference clock outputs (REF0, REF1) are provided.

All output frequencies are generated from a 14.318-MHZ crystalinput. A reference clock input can be provided at the X1 inputinstead of a crystal input.

Two phase-locked loops (PLLs) are used to generate the host clockfrequency and the 48-MHz clock frequency. On-chip loop filters andinternal feedback eliminate the need for external components. ThePCI-clock frequency and floppy controller frequency are deriveddirectly from the host-clock frequency and USB frequency,respectively. The PLL circuit can be bypassed in the test mode (i.e.,SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.

The host- and PCI-clock outputs provide low-skew/low-jitter clocksignals for reliable clock operation. All outputs are 3 state and areenabled via OE.

Because the CDC9843 is based on PLL circuitry, it requires astabilization time to achieve phase-lock of the PLL. Thisstabilization time is required following power up and application ofa fixed-frequency, fixed-phase signal at the X1, as well as followingany changes to the OE or SELn inputs.

Title: PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: CLOCK SYNTHESIZER/DRIVER
Orderable Devices: CDC9843DW

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