CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS

SCAS546B - NOVEMBER 1995 - REVISED MAY 1996

features

• Provides System Clock Solution for Pentium^TM/82430X/82430VX and PentiumPro 82440FX Chipsets
• Four Host-Clock Outputs With Programmable Frequency (50 MHz, 60 MHz and 66 MHz)
• Six PCI Clock Outputs at Half-CPU Frequency
• One 48-MHz Universal Serial Bus (USB) Clock Output
• Three 14.318-MHz Reference Clock Outputs
• All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input
• LVTTL-Compatible Inputs and Outputs
• Internal Loop Filters for Phase-Locked Loops Eliminate the Need for External Components
• Operates at 3.3 V_CC
• Packaged in Plastic Small-Outline Package

  Pentium is a trademark of Intel Corporation.

description

The CDC9842 is a high-performance clock synthesizer/driver thatgenerates the system clocks necessary to supportPentium^TM/82430X/82430VX and PentiumPro 82440FX chipsets.Four host-clock outputs (HCLKn) are programmable to one of threefrequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 controlinputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPUclock outputs and are delayed 1 ns to 4 ns from the rising edge ofthe CPU clock. In addition, a universal serial bus (USB) clock outputat 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0,REF1, REF2) are provided.

All output frequencies are generated from a 14.318-MHZ crystalinput. A reference clock can be provided at the X1 input instead of acrystal input.

Two phase-locked loops (PLLs) are used to generate the host clockfrequency and the 48-MHz clock frequency. On-chip loop filters andinternal feedback eliminate the need for external components. ThePCI-clock frequency is derived directly from the host-clockfrequency. The PLL circuit can be bypassed in the TEST mode (i.e.,SEL0 = SEL1 = H) to distribute a test clock provided at the X1 input.

The host- and PCI-clock outputs provide low-skew/low-jitter clocksignals for reliable clock operation. All outputs are 3 state and areenabled via OE.

Because the CDC9842 is based on PLL circuitry, it requires astabilization time to achieve phase-lock of the PLL. Thisstabilization time is required following power up and application ofa fixed-frequency, fixed-phase signal at the X1 input, as well asfollowing any changes to the OE or SELn inputs.

View more information about generic part numbers:CDC9842

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