



SCAS502C - APRIL 1995 - REVISED MAY 1996
The CDC913 is a high-performance clock generator with integrateddual 1-to-4 buffers, which simplifies clock system design for PCmotherboards. The CDC913 consists of a crystal oscillator, twophase-locked loops (PLL), and two 1-to-4 buffers. The CDC913generates all frequencies using a single 14.318-MHz crystal.
The CPUCLK output is programmable to one of three frequencies (50MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 inputs. PCICLK outputsa 33-MHz clock, independent of the CPUCLK frequency. REFCLK providesa buffered copy of the 14.318-MHz reference. The oscillator and PLLsin the CDC913 are bypassed when in the TEST mode, i.e., SEL1 = SEL0 =H. When in the TEST mode, a test clock can be driven over the X1input and buffered out from the PCICLK, CPUCLK, and REFCLK outputs.
Outputs 1Yn and 2Yn are 3-state outputs and are enabled via
islow, the outputs are enabled.
Since the CDC913 is based on PLL circuitry, it requires astabilization time to achieve phase lock of the PLL. Thisstabilization time is required following power up and application ofa fixed-frequency, fixed-phase signal at the X1 input, and followingany changes to the SELn inputs.
View more information about generic part numbers:CDC913
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.



