74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

SCAS499A - DECEMBER 1986 - REVISED APRIL 1996

features

Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)

EPIC is a trademark of Texas Instruments

description

This device contains two independent positive-edge-triggeredD-type flip-flops. A low level at the preset () or clear () input sets or resets the outputsregardless of the levels of the other inputs. When and are inactive (high), data at thedata (D) input that meets the setup-time requirements are transferredto the outputs on the low-to-high transition of the clock (CLK)pulse. Clock triggering occurs at a voltage level and is not directlyrelated to the rise time of the clock pulse. Following the hold-timeinterval, data at the D input may be changed without affecting thelevels at the outputs.

The 74AC11074 is characterized for operation from -40°C to85°C.

Title: DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
Product Family: D-TYPE FLIP-FLOPS
Device Functionality: DUAL D-TYPE FLIP-FLOP
Orderable Devices: 74AC11074D, 74AC11074DR, 74AC11074N, 74AC11074PWLE

View the complete PDF datasheet: scas499a.pdf (87 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74AC11074

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