SCAS458D - DECEMBER 1994 - REVISED APRIL 1996
The CDC9841 is a high-performance clock synthesizer/driver thatgenerates all required clock signals necessary for a high-performancePC motherboard. The four central processing unit (CPU) clock outputs(PCLKn) are programmable to one of three frequencies (50 MHz, 60 MHz,or 66 MHz) via the SEL0 and SEL1 control inputs. The sixperipheral-component-interconnect (PCI) clock outputs (BCLKn) arehalf the frequency of PCLKn and are delayed 1 ns to 4 ns from therising edge of the CPU clock. In addition, the four fixed-frequencyoutputs provide a 24-MHz clock (CLK24), a 12-MHz clock (CLK12), andtwo buffered copies of the 14.318-MHz input reference (REF0, REF1).
The CDC9841 generates all output frequencies from a 14.31818-MHzcrystal input. A reference clock can be provided at X1 instead of acrystal input.
Two phase-lock loops (PLLs) generate the CPU clock frequency andthe 24-MHz clock frequency. On-chip loop filters and internalfeedback eliminate the need for external components. The PCI and12-MHz clock frequencies are derived from the base CPU and 24-MHzclock frequencies, respectively. The PLL circuit can be bypassed inthe TEST mode (i.e., SEL0 = SEL1 = H) to distribute a test clockprovided at the X1 input. Because the CDC9841 is based on PLLcircuitry, it requires a stabilization time to achieve phase lock ofthe PLL. This stabilization time is required following power up andapplication of a fixed-frequency, fixed-phase signal at the X1 input,as well as following any changes to the SELn inputs.
PCLKn and BCLKn provide low-skew/low-jitter clock signals forreliable clock operation. All outputs are 3 state and are enabled viaOE.
View more information about generic part numbers:CDC9841
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