54AC11109, 74AC11109 WITH CLEAR AND PRESET

SCAS450 - MARCH 1987 - REVISED APRIL 1993

features

Flow-Through Architecture Optimizes PCB Layout
Center-Pin V_CC and GND Configurations Minimize High-Speed Switching Noise
EPIC^TM (Enhanced-Performance Implanted CMOS) 1-m Process
500-mA Typical Latch-Up Immunity at 125°C
ESD Protection Exceeds 2000 V, MIL STD-883C Method 3015
Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

EPIC is a trademark of Texas Instruments

description

These devices contain two independent J-K\ positive-edge-triggeredflip-flops. A low level at the preset () or clear () inputs sets or resets the outputsregardless of the levels of the other inputs. When preset and clearare inactive (high), data at the J and K\ inputs meeting the setuptime requirements are transferred to the outputs on thepositive-going edge of the clock pulse. Clock triggering occurs at avoltage level and is not directly related to the rise time of theclock pulse. Following the hold time interval, data at the J and K\inputs may be changed without affecting the levels at the outputs.These versatile flip-flops can perform as toggle flip-flops bygrounding K\ and tying J high. They also can perform as D-typeflip-flops by tying the J and K\ inputs together.

The 54AC11109 is characterized for operation over the fullmilitary temperature range of -55°C to 125°C. The 74AC11109is characterized for operation from -40°C to 85°C.

Title: DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND
Product Family: OTHER FLIP-FLOPS
Device Functionality: DUAL J-K FLIP-FLOP
Orderable Devices: 74AC11109D, 74AC11109DR, 74AC11109N

View the complete PDF datasheet: scas450.pdf (83 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:74AC11109

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