CDC582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS446B - JULY 1994 - REVISED FEBRUARY 1996

features

Low Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs
Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs
Application for Synchronous DRAMs
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in 52-Pin Quad Flatpack
EPIC-IIB is a trademark of Texas Instruments Incorporated.

description

The CDC582 is a high-performance, low-skew, low-jitter clockdriver. It uses a phase-lock loop (PLL) to precisely align thefrequency and phase of the clock output signals to the differentialLVPECL clock (CLKIN, ) inputsignals. It is specifically designed to operate at speeds from 50 MHzto 100 MHz or down to 25 MHz on outputs configured as half-frequencyoutputs. The CDC582 operates at 3.3-V V_CC.

The feedback input (FBIN) synchronizes the frequency of the outputclocks with the input clock (CLKIN, ) signals. One of the twelve output clocks must be fedback to FBIN for the PLL to maintain synchronization between thedifferential CLKIN and inputs and the outputs. The output used as feedback is synchronizedto the same frequency as the clock (CLKIN and ) inputs.

The Y outputs can be configured to switch in phase and at the samefrequency as differential clock inputs (CLKIN and ). Select(SEL1, SEL0) inputs configure up to nine Y outputs, in banks ofthree, to operate at one-half or double the differential clock inputfrequency, depending upon the feedback configuration (see Tables 1and 2). All output signal duty cycles are adjusted to 50% independentof the duty cycle at the input clocks.

Output-enable () is providedfor output control. When ishigh, the outputs are in the low state. When is low, the outputs are active. isnegative-edge triggered and can be used to reset the outputsoperating at half frequency. TEST is used for factory testing of thedevice and can be used to bypass the PLL. TEST should be strapped toGND for normal operation.

Unlike many products containing a PLL, the CDC582 does not requireexternal RC networks. The loop filter for the PLL is included onchip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC582 requires astabilization time to achieve phase lock of the feedback signal tothe reference signal. This stabilization time is required followingpower up and application of a fixed-frequency, fixed-phase signal atCLKIN and CLKIN\, as well as following any changes to the PLLreference or feedback signal. Such changes occur upon change of SEL1and SEL0, enabling the PLL via TEST, and upon enable of all outputsvia .

The CDC582 is characterized for operation from 0°C to70°C.

Title: 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: CLOCK DRIVER
Orderable Devices: CDC582PAH

View the complete PDF datasheet: scas446b.pdf (134 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:CDC582

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.