CDC351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS

SCAS441C - FEBUARY 1994 - REVISED NOVEMBER 1995

features

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
LVTTL-Compatible Inputs and Outputs
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Distributes One Clock Input to Ten Outputs
Distributed V_CC and Ground Pins Reduce Switching Noise
High-Drive Outputs (-32-mA I_OH, 32-mA I_OL)
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages
EPIC-IIB is a trademark of Texas Instruments Incorporated.

description

The CDC351 is a high-performance clock-driver circuit thatdistributes one input (A) to ten outputs (Y) with minimum skew forclock distribution. The output-enable () input disables the outputs to ahigh-impedance state. The CDC351 operates at nominal 3.3-VV_CC.

The propagation delays are adjusted at the factory using the P0and P1 pins. The factory adjustments ensure that the part-to-partskew is minimized and is kept within a specified window. Pins P0 andP1 are not intended for customer use and should be connected to GND.

The CDC351 is characterized for operation from 0°C to70°C.

Title: 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
Product Family: OTHER DIGITAL LOGIC
Device Functionality: BUFFER CLOCK DRIVER
Orderable Devices: CDC351DBLE, CDC351DW, CDC351DWR

View the complete PDF datasheet: scas441c.pdf (102 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:CDC351

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