SN74ALVC7804 512 x 18 FIRST-IN, FIRST-OUT MEMORY SCAS432 - JANUARY 1995

features

Operates at 3-V to 3.6-V V_CC
Load Clock and Unload Clock Can Be Asynchronous or Coincident
Low-Power Advanced CMOS Technology
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty Flag
Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously
Data Rates From 0 to 40 MHz
3-State Outputs
Pin Compatible With SN74ACT7804
Packaged in Shrink Small-Outline 300-mil Package (DL) Using 25-mil Center-to-Center Spacing

description

A FIFO memory is a storage device that allows data to be writteninto and read from its array at independent data rates. TheSN74ALVC7804 is an 18-bit FIFO with high speed and fast access times.Data is processed at rates up to 40 MHz with access times of 18 ns ina bit-parallel format. The SN74ALVC7804 is designed for 3-V to 3.6-VV_CC operation.

Data is written into memory on a low-to-high transition of theload clock (LDCK) and is read out on a low-to-high transition of theunload clock (UNCK). The memory is full when the number of wordsclocked in exceeds the number of words clocked out by 512. When thememory is full, LDCK has no effect on the data residing in memory.When the memory is empty, UNCK has no effect.

Status of the FIFO memory is monitored by the full (), empty (), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The output is low when the memory is full and high when thememory is not full. The output is low when the memory is empty and high when it is not empty.The HF output is high whenever the FIFO contains 256 or more wordsand is low when it contains 255 or less words. The AF/AE status flagis a programmable flag. The first one or two low-to-high transitionsof LDCK after reset are used to program the almost-empty offset value(X) and the almost-full offset value (Y), if program enable () is low. The AF/AE flag is highwhen the FIFO contains X or less words or (512 minus Y) or morewords. The AF/AE flag is low when the FIFO contains between (X plus1) and (511 minus Y) words.

A low level on the reset () resets the internal stack pointers and sets high, AF/AE high, HF low, and low. The Q outputs are not resetto any specific logic level. The FIFO must be reset upon power up.The first word loaded into empty memory causes to go high and the data to appearon the Q outputs. The data outputs are in the high-impedance statewhen the output-enable () ishigh.

Title: 512 X 18 FIRST-IN, FIRST-OUT
Product Family: STROBED FIFOS
Device Functionality: 512 X 18
Orderable Devices: SN74ALVC7804-25DL, SN74ALVC7804-40DL, SN74ALVC7804-25DL, SN74ALVC7804-40DL

View the complete PDF datasheet: scas432.pdf (157 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC7804, SN74ALVC7804-25, SN74ALVC7804-40

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