SCAS381 - D3199, AUGUST 1988 - REVISED APRIL 1993
m Process EPIC is a trademark of Texas Instruments Incorporated.
This synchronous, presettable 4-bit decade counter features aninternal carry look-ahead circuitry for application in high-speedcounting designs. Synchronous operation is provided by having allflip-flops clocked simultaneously so that the outputs changecoincident with each other when so instructed by the count-enableinputs and internal gating. This mode of operation eliminates theoutput counting spikes that are normally associated with asynchronous(ripple-clock) counters; however, counting spikes may occur on theripple-carry (RCO) output. A buffered clock (CLK) input triggers thefour flip-flops on the rising (positive-going) edge of theclock-input waveform.
These counters are fully programmable in that they may be presetto any number between 0 and 9. As presetting is synchronous, settingup a low level at the load (
)input disables the counter and causes the outputs to agree with thesetup data after the next clock pulse regardless of the levels of theenable inputs.
If one of these decade counters is preset to a number between 10and 15 or assumes such an invalid state when power is applied, itprogresses to the normal sequence within two counts as shown in thestate diagram.
The clear function for the 74AC11162 is synchronous, and a lowlevel at the clear (
)input drives all four of the flip-flop outputs low after the nextlow-to-high transition of the clock regardless of the levels on thecount-enable (ENP and ENT) inputs. This synchronous clear allows thecount length to be modified easily by decoding the Q outputs for themaximum count desired. The active-low output of the gate used fordecoding is connected to the clear input to synchronously clear thecounter to 0000 (LLLL on the Q outputs).
The carry look-ahead circuitry provides for cascading counters forn-bit synchronous applications without additional gating.Instrumental in accomplishing this function are two count-enable (ENPand ENT) inputs and a ripple-carry (RCO) output. Both ENP and ENTmust be high to count, and ENT is fed foward to enable RCO. RCO thusenabled produces a high-level pulse while the count is 9 (HLLH). Thishigh-level overflow ripple-carry pulse can be used to enablesuccessive cascaded stages. Transitions at the ENP or ENT inputs areallowed regardless of the level of the clock input.
These counters feature fully independent clock circuits. Changesat control inputs (ENP, ENT, or ) that modify the operating mode have no effect on thecontents of the counter until clocking occurs. The function of thecounter (whether enabled, disabled, loading, or counting) is dictatedsolely by the conditions meeting the setup and hold times.
The 74AC11162 is characterized for operation from -40°C to85°C.
View more information about generic part numbers:74AC11162
Go to the Engineering Design Center to locate information on other TI Semiconductor devices.