CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B - FEBRUARY 1993 - REVISED FEBRUARY 1996

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features

• Low Output Skew for Clock-Distribution and Clock-Generation Applications
• Operates at 3.3-V V_CC
• Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs
• Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
• No External RC Network Required
• External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs
• Application for Synchronous DRAMs
• Outputs Have Internal 26- Series Resistors to Dampen Transmission-Line Effects
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Distributed V_CC and Ground Pins Reduce Switching Noise
• Packaged in 52-Pin Quad Flatpack

  EPIC-IIB is a trademark of Texas Instruments Incorporated.

   

description

The CDC2582 is a high-performance, low-skew, low-jitter clockdriver. It uses a phase-lock loop (PLL) to precisely align thefrequency and phase of the clock output signals to the differentialLVPECL clock (CLKIN, ) inputsignals. It is specifically designed to operate at speeds from 50 MHzto 100 MHz or down to 25 MHz on outputs configured as half-frequencyoutputs. Each output has an internal 26- series resistor thatimproves the signal integrity at the load. The CDC2582 operates at3.3-V V_CC.

The feedback input (FBIN) synchronizes the frequency of the outputclocks with the input clock (CLKIN, ) signals. One of the twelve output clocks must be fedback to FBIN for the PLL to maintain synchronization between thedifferential CLKIN and inputs and the outputs. The output used as feedback issynchronized to the same frequency as the clock (CLKIN and ) inputs.

The Y outputs can be configured to switch in phase and at the samefrequency as differential clock inputs (CLKIN and ). Select (SEL1, SEL0) inputsconfigure up to nine Y outputs, in banks of three, to operate atone-half or double the differential clock input frequency, dependingupon the feedback configuration (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independentof the duty cycle at the input clocks.

Output-enable () is providedfor output control. When ishigh, the outputs are in the low state. When is low, the outputs are active. isnegative-edge triggered and can be used to reset the outputsoperating at half frequency. TEST is used for factory testing of thedevice and can be used to bypass the PLL. TEST should be strapped toGND for normal operation.

Unlike many products containing a PLL, the CDC2582 does notrequire external RC networks. The loop filter for the PLL is includedon chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2582 requires astabilization time to achieve phase lock of the feedback signal tothe reference signal. This stabilization time is required followingpower up and application of a fixed-frequency, fixed-phase signal atCLKIN and , as well asfollowing any changes to the PLL reference or feedback signal. Suchchanges occur upon change of SEL1 and SEL0, enabling the PLL viaTEST, and upon enable of all outputs via .

The CDC2582 is characterized for operation from 0°C to70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2582 has afrequency range of 100 MHz to 200 MHz, twice the operating frequencyrange of the CDC2582 outputs. The output of the VCO is divided by 2and by 4 to provide reference frequencies with a 50% duty cycle ofone-half and one-fourth the VCO frequency. SEL0 and SEL1 determinewhich of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete thePLL. The VCO operates such that the frequency of this output matchesthat of the CLKIN/ signals. Inthe case that a VCO/2 output is wired to FBIN, the VCO must operateat twice the CLKIN/frequency,resulting in device outputs that operate at the same or one-half theCLKIN/ frequency. Ifa VCO/4 output is wired to FBIN, the device outputs operate at thesame or twice the CLKIN/frequency.

output configuration A

Output configuration A is valid when any output configured as a1× frequency output in Table 1 is fed back to FBIN. Thefrequency range for the differential clock input is 50 MHz to 100 MHzwhen using output configuration A. Outputs configured as 1/2×outputs operate at half the input clock frequency, while outputsconfigured as 1× outputs operate at the same frequency as thedifferential clock input.

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a1× frequency output in Table 2 is fed back to FBIN. Thefrequency range for the differential clock inputs is 25 MHz to 50 MHzwhen using output configuration B. Outputs configured as 1×outputs operate at the input clock frequency, while outputsconfigured as 2× outputs operate at double the frequency of thedifferential clock inputs.

NOTE: n = 1, 2, 3

View more information about generic part numbers:CDC2582

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