SCAS378E - APRIL 1994 - REVISED JANUARY 1998
Parallel-Terminated Transmission LinesEPIC-IIB is a trademark of Texas Instruments Incorporated.
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50- transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.
Output-enable (OE\) is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. CLR\ is negative-edge triggered and can be used to reset the outputs operating at half frequency. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.
The CDC536 is characterized for operation from 0°C to 70°C.
The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0 and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN, the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKIN frequency.
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs configured as 1× outputs operate at the same frequency as the CLKIN input.
NOTE: n = 1, 2, 3
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B. Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs operate at double the frequency of the CLKIN input.
NOTE: n = 1, 2, 3
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