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Data Sheet Abstract

SN74ALVC162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS376 - MARCH 1994


features

 

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description

This 18-bit universal bus transceiver is designed for 2.7-V to3.6-V VCC operation.

The SN74ALVC162601 combines D-type latches and D-type flip-flopsto allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA),and clock (CLKAB and CLKBA) inputs. The clock can be controlled bythe clock-enable ( and ) inputs. For A-to-B data flow, thedevice operates in the transparent mode when LEAB is high. When LEABis low, the A data is latched if CLKAB is held at a high or low logiclevel. If LEAB is low, the A-bus data is stored in thelatch/flip-flop on the high-to-low transition of CLKAB. Output enable is active low.When is low, theoutputs are active. When ishigh, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses , LEBA, CLKBA, and .

The B-port outputs, include 25- series resistors to reduce overshoot and undershoot.

The SN74ALVC162601 is available in TI's shrink small-outline (DL)and thin shrink small-outline (DGG) packages, which provide twice theI/O pin count and functionality of standard small-outline packages inthe same printed-circuit-board area.

The SN74ALVC162601 is characterized for operation from -40°Cto 85°C.


Title: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: BUS TRANSCEIVERS
Orderable Devices: SN74ALVC162601DL, SN74ALVC162601DLR

View the complete PDF datasheet: scas376.pdf (88 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74ALVC162601

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