SCAS337B - FEBRUARY 1993 - REVISED NOVEMBER 1995
Series Resistors to Dampen Transmission-Line Effects EPIC-IIB is a trademark of Texas Instruments Incorporated.
The CDC2586 is a high-performance, low-skew, low-jitter clockdriver. It uses a phase-lock loop (PLL) to precisely align, in bothfrequency and phase, the clock output signals to the clock input(CLKIN) signal. It is specifically designed for use with popularmicroprocessors operating at speeds from 50 MHz to 100 MHz or down to25 MHz on outputs configured for half-frequency operation. Eachoutput has an internal 26-series resistor that improves the signal integrity at the load. TheCDC2586 operates at nominal 3.3-V VCC.
The feedback input (FBIN) synchronizes the output clocks infrequency and phase to CLKIN. One of the twelve output clocks must befed back to FBIN for the PLL to maintain synchronization betweenCLKIN and the outputs. The output used as feedback is synchronized tothe same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the samefrequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Youtputs, in banks of three, to operate at one-half or double theCLKIN frequency depending on which output is fed back to FBIN (seeTables 1 and 2). All output signal duty cycles are adjusted to 50%independent of the duty cycle at CLKIN.
Output-enable (
) providesoutput control. When ishigh, the outputs are in the high-impedance state. When 
isnegative-edge triggered and can be used to reset the outputsoperating at half frequency. TEST is used for factory testing of thedevice and can be used to bypass the PLL. TEST should be strapped toGND for normal operation.
Unlike many products containing PLLs, the CDC2586 does not requireexternal RC networks. The loop filter for the PLL is included onchip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2586 requires astabilization time to achieve phase lock of the feedback signal tothe reference signal. This stabilization time is required followingpower up and application of a fixed-frequency, fixed-phase signal atCLKIN, as well as following any changes to the PLL reference orfeedback signals. Such changes occur upon change of the selectinputs, enabling of the PLL via TEST, and upon enable of all outputsvia .
The CDC2586 is characterized for operation from 0°C to70°C.
The voltage-controlled oscillator (VCO) used in the CDC2586 PLLhas a frequency range of 100 MHz to 200 MHz, twice the operatingfrequency range of the CDC2586 outputs. The output of the VCO isdivided by two and four to provide reference frequencies with a 50%duty cycle of one-half and one-fourth the VCO frequency. The SEL0 andSEL1 inputs select which of the two signals are buffered to each bankof device outputs.
One device output must be externally wired to FBIN to complete thePLL. The VCO operates such that the frequency and phase of thisoutput matches that of the CLKIN signal. In the case that a VCO/2output is wired to FBIN, the VCO must operate at twice the CLKINfrequency resulting in device outputs that operate at either the sameor one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN,the device outputs operate at twice or the same as the CLKINfrequency.
Output configuration A is valid when any output configured as a 1frequency output in Table 1 is fed back to FBIN. The input frequencyrange for CLKIN is 50 MHz to 100 MHz when using output configurationA. Outputs configured as 1/2 outputs operate at half the CLKINfrequency, while outputs configured as 1 outputs operate at the samefrequency as CLKIN.
Output configuration B is valid when any output configured as a 1frequency output in Table 2 is fed back to FBIN. The input frequencyrange for CLKIN is 25 MHz to 50 MHz when using output configurationB. Outputs configured as 1 outputs operate at the CLKIN frequency,while outputs configured as 2 outputs operate at double the frequencyof CLKIN.
View more information about generic part numbers:CDC2586
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