CDC305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A - JUNE 1990 - REVISED NOVEMBER 1995
features
- Replaces SN74AS305
- Maximum Output Skew of 1 ns
- Maximum Pulse Skew of 1ns
- TTL-Compatible Inputs and Outputs
- Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
- Package Options Include Plastic Small-Outline (D) Package and Standard Plastic (N) 300-mil DIPs
description
The CDC305 contains eight flip-flops designed to have low skewbetween outputs. The eight outputs (four in-phase with CLK and fourout-of-phase) toggle on successive CLK pulses. Preset () and clear () inputs are provided to set the Qand Q\ outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters tsk(o)and tsk(p) to ensure performance as a clock driver when adivide-by-two function is required.
The CDC305 is characterized for operation from 0°C to70°C.
Title: OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
Product Family: OTHER DIGITAL LOGIC
Device Functionality: CLOCK DRIVER
Orderable Devices: CDC305D, CDC305DR, CDC305N
View the complete PDF datasheet: scas326a.pdf (86 K Bytes) (Requires Acrobat Reader 3.x)View more information about generic part numbers:CDC305
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