CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321F - SEPTEMBER 1993 - REVISED AUGUST 1996
features
- Low-Output Skew for Clock-Distribution Applications
- Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs
- Distributes Differential Clock Inputs to Nine Differential Clock Outputs
- Output Reference Voltage, VREF, Allows Distribution From a Single-Ended Clock Input
- Single-Ended LVPECL-Compatible Output Enable
- Packaged in Plastic Chip Carrier
description
The differential LVPECL clock-driver circuit distributes one pairof differential LVPECL clock inputs (CLKIN, ) to nine pairs of differentialclock (Y, Y\) outputs with minimum skew for clock distribution. It isspecifically designed for driving 50- transmission lines.
When the output-enable (
) islow, the nine differential outputs switch at the same frequency asthe differential clock inputs. When is high, the nine differential outputs are in staticstates (Y outputs are in the low state, Y\ outputs are in the highstate).
The VREF output can be strapped to the input for a single-ended CLKINinput.
The CDC111 is characterized for operation from 0°C to70°C.
Title: 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
Product Family: OTHER DIGITAL LOGIC
Device Functionality: CLOCK BUFFER
Orderable Devices: CDC111FN, CDC111FNR
View the complete PDF datasheet: scas321f.pdf (87 K Bytes) (Requires Acrobat Reader 3.x)View more information about generic part numbers:CDC111
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