SN74LVC2952 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

SCAS311A - JANUARY 1993 - REVISED JULY 1995

features

EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages
EPIC is a trademark of Texas Instruments Incorporated.

description

This octal bus transceiver and register is designed for 2.7-V to 3.6-V V_CC operation; it can interface to a 5-V system environment.

The SN74LVC2952 consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC2952 is characterized for operation from -40°C to 85°C

Title: OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
Product Family: UNIVERSAL BUS TRANSCEIVERS (UBTS)
Device Functionality: BUS TRANSCEIVER
Orderable Devices: SN74LVC2952DBLE, SN74LVC2952DW, SN74LVC2952DWR

View the complete PDF datasheet: scas311a.pdf (92 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVC2952

Go to the Engineering Design Center to locate information on other TI Semiconductor devices.