SN74LVC823A 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SCAS305E - MARCH 1993 - REVISED JANUARY 1998

features

EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
Power Off Disables Inputs/Outputs, Permitting Live Insertion
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per JESD 17
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

EPIC is a trademark of Texas Instruments Incorporated.

description

This 9-bit bus-interface flip-flop is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN\) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN\ high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR\) input low causes the nine Q outputs to go low, independently of the clock.

A buffered output-enable (OE\) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC823A is characterized for operation from -40°C to 85°C.

Title: 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Product Family: D-TYPE (3-STATE) FLIP-FLOPS
Device Functionality: 9-BIT BUS FLIP-FLOP
Orderable Devices: SN74LVC823ADBLE, SN74LVC823ADW, SN74LVC823ADWR, SN74LVC823APWLE

View the complete PDF datasheet: scas305e.pdf (101 K Bytes) (Requires Acrobat Reader 3.x)

View more information about generic part numbers:SN74LVC823A

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