SN74LVC543 OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

SCAS299A - JANUARY 1993 - REVISED JULY 1995

features

• EPIC^TM (Enhanced-Performance Implanted CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
• Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages

  EPIC is a trademark of Texas Instruments Incorporated.

description

This octal registered transceiver is designed for 2.7-V to 3.6-V V_CC operation.

The SN74LVC543 contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB\) input must be low to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ places the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow for B to A is similar to that of A to B but uses CEBA\, LEBA\, and OEBA\.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVC543 is characterized for operation from -40°C to 85°C

View more information about generic part numbers:SN74LVC543

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